1. Field of the Invention
The present invention relates to a stacked film patterning method and a gate electrode forming method and more particularly to the stacked film patterning method to be used in manufacturing of, for example, a TFT (Thin Film Transistor) substrate making up a liquid crystal display device and to be used when a stacked film with a two-layer structure configured by stacking a metal film on a silicon film is formed as, for example, an electrode layer and to the method of forming the gate electrode of, for example, the TFT.
2. Description of the Related Art
Conventionally, a structure of a TFT is classified into two types, one being of a bottom-gate type to be used mainly in an amorphous silicon TFT and the other being of a top-gate type to be used mainly in a polycrystalline silicon TFT. As a gate electrode for the top-gate TFT, a single layer of each of a silicon film, metal film, metal silicide film is used, however, additional technology is proposed in which the gate electrode is constructed by using a stacked film made up of a metal film or metal silicide film deposited on a silicon film in order to increase reliability and to use resistors of lower resistance.
That is, the technical proposal includes the use of a stacked film made up of, for example, a metal silicide film formed on a polycrystalline silicon film (for example, Japanese Patent Application Laid-open No. Hei 05-235353), or a stacked film made up of a metal film or metal silicide film formed on a micro-crystal silicon film (for example, No. Hei 11-307777). In the above Japanese Patent Application Laid-open Nos. Hei 05-235353 and Hei 11-307777, when a gate electrode is formed by patterning, a dry etching process is carried out on both a metal material making up a metal film or metal silicide film serving as an upper layer and a silicon material making up a polycrystalline silicon film or micro-crystal silicon film serving as a lower layer.
However, the metal material includes a material having a low etching rate for dry etching or the material being prone to produce trash caused by a reaction product accumulated in a chamber during dry etching and, therefore, in some cases, use of a wet etching method rather than the dry etching method at a time when patterning is performed on the metal film is advantageous in terms of productivity.
For example, in the case of a chromium film, etching rate by dry etching is about 40 nm/min, whereas an etching rate by wet etching using, for example, an ammonium cerium nitrate etching solution is about 100 nm/min. Therefore, when a stacked film made up of a chromium film is formed on a silicon film and a gate electrode is formed by patterning, by using the wet etching method to etch the chromium film and by using the dry etching method to etch the silicon film, a throughput (processing capability) can be raised.
However, the method in which, after the wet-etching of the chromium film, the silicon film is dry etched has a problem; that is, an etching residue occurring after the wet-etching of the chromium film inhibits the dry-etching of the silicon film and, as a result, etching uniformity deteriorates and a residue of silicon occurs. The problem that etching uniformity deteriorates and the residue occurs when a gate electrode of a top-gate type polycrystalline silicon TFT is formed is explained together with an initial stage of manufacturing TFTs. First, as shown in FIG. 7A, a front-end insulating film 102 made of silicon dioxide or silicon nitride is deposited by plasma CVD so as to have a film thickness of about 300 nm on a glass substrate 101.
Next, an amorphous silicon film is deposited by plasma CVD on the front-end insulating film 102 so as to have its film thickness of 50 nm. Then, a polycrystalline silicon film 104 is formed by radiating, for example, an excimer laser to crystallize the amorphous silicon film. Then, the polycrystalline silicon film 104 is patterned by the dry-etching method using the resist as a mask to form an island structure which serves as an active layer of the TFT.
Next, a gate insulating film 105 made of a silicon oxide film with its film thickness of about 100 nm is deposited by the plasma CVD on the polycrystalline silicon film 104 patterned so as to have the island structure. Then, an n-type micro-crystal silicon film 106 with its film thickness of about 100 nm is formed which contains phosphorus (P) as an impurity and serves as a lower layer of a gate electrode 109. Next, a chromium film 107 is deposited so as to have its film thickness of about 200 nm by spattering, which serves as an upper layer of the gate electrode 109.
Then, the upper layer of the gate electrode 109 is formed by patterning the chromium film 107 and by wet-etching using, for example, an ammonium cerium nitrate etching solution and using the resist film 108 as a mask. Now, on a surface of the exposed micro-crystal silicon film 106 occur, in an ununiform state, residues of metal chromium remaining after the wet-etching and residual substances 110 being chromium silicide which are compounds of chromium with silicon.
Next, as shown in FIG. 7B, the lower layer of the gate electrode 109 is formed by patterning the micro-crystal silicon film 106 using a dry-etching method. However, in a state in which the residues of metal chromium and/or the residual substances 110 being chromium silicide are left on the micro-crystal silicon film 106, these substances act as a mask which impairs the progress of smooth etching. This causes the uniformity of etching to deteriorate and cylindrical residues 111 of silicon to occur. These residues 111 of silicon act as a barrier in an impurity implanting process and contact hole forming process to be performed thereafter, which inhibits the formation of a TFT having excellent characteristics.
To solve this problem, when a gate electrode is formed by patterning a stacked film made up of a silicon film and metal film and by combined use of the wet-etching and dry-etching methods, in order to prevent etching failures, technology is proposed which includes a process of removing residual substances that inhibit the smooth etching is required after the wet-etching of the metal film and before the dry-etching of the silicon film.
The method to remove such residual substances as described above includes a method of performing an etching process using plasma of, for example, oxygen gas (for example, Japanese Patent Application Laid-open No. Hei 05-283427), a method of performing a wet-etching process using a solution including hydrofluoric acid or of performing a sputter-etching process using plasma of inert gas such as argon or a like (for example, Japanese Patent Application Laid-open No. Hei 06-283547), and a method of performing an etching process using plasma of a mixed gas including methane trifluoride (CHF3) gas and oxygen gas (for example, Japanese Patent Application Laid-open No. 2001-274411).
The purpose of the technologies disclosed in the above Japanese Patent Application Laid-open Nos. Hei 05-283427, Hei 06-283547, and 2001-274411 is to prevent the occurrence of etching failures caused by residual substances when, in a bottom-gate type amorphous silicon TFT, an n-type amorphous silicon film of a back channel is to be removed by a dry-etching method after source/drain electrodes made of a metal film is formed by a wet-etching method.
However, the conventional technologies have problems. A first problem to be solved is that, in the above conventional technology, residual substances remaining after etching a metal film cannot be removed satisfactorily and, as a result, etching uniformity of a silicon film deteriorates and residues of etching occur. For example, even if the technology disclosed in the Japanese Patent Application Laid-open No. Hei 05-283427 is used, it is impossible to remove residual substances by etching.
That is, since a vapor pressure of an oxide of metal or silicon is low, the removal of residual substances by etching using only plasma of oxygen is impossible. Moreover, by the repetition of both the oxygen plasma processing and subsequent silicon film etching processes, oxygen and an residual amount of gas used for etching the silicon film are mixed and, as a result, though the effect of removing residual substances appears, the residual amount of the gas used for etching the silicon film, decreases during the evacuation and oxygen plasma processing to be carried out before subsequent processing on a substrate starts and the capability of removing the residual substances becomes unstable and the effect of removing residual substances decreases with passage of processing time.
Also, when the technology disclosed in the above Japanese Patent Application Laid-open No. 2001-274411 is applied to the formation of a gate electrode of a top-gate type polycrystalline TFT, the residual substances cannot be fully removed in patterning of a stacked film made up of a metal film formed on a polycrystalline silicon film or micro-crystal silicon film having a crystalline property being higher than that of amorphous silicon. That is, the polycrystalline silicon film or micro-crystal silicon film are films made up of small crystals gathered together on which fine concave and/or convex portions derived from the crystalline property appear. Additionally, in a region in which the polycrystalline silicon film serving as the active layer exists with the gate insulating film being interposed between the micro-crystal silicon film and the polycrystalline silicon film under the gate electrode of the top-gate polycrystalline TFT, concave and/or convex portions occurring on the surface of the silicon film of the gate electrode are big in size and complicated in shape.
Thus, when the metal film formed on the silicon film on the surface of which fine concave and/or convex portions exist is formed by patterning using the wet-etching method, many residual substances occur on the exposed surface of the silicon film and non-silicidized residual substances in a metal state increase. If residual substances increase, even by the etching process using plasma of a mixed gas including CHF3 gas and oxygen gas, it is impossible to fully remove residual substances. For example, when the metal film is a chromium film, since a vapor pressure of a fluoric compound with chromium is low, almost no residual substances left in a metal state can be removed.
A second problem to be solved is that the above conventional technology causes a decrease in throughput. For example, in the conventional technology disclosed in the above Japanese Patent Application Laid-open No. Hei 06-283547, successive processes of the wet-etching process using the solution including hydrofluoric acid and the subsequent process of etching the silicon film are impossible, which causes a decrease in throughput.
Moreover, a third problem to be solved is that, in the conventional technology, etching of a region that should be left without being etched or a similar unexpected matter occurs; that is, by the conventional technology, exact removal of residual substances is impossible. For example, in the conventional technology disclosed in the above Japanese Patent Application Laid-open No. Hei 06-283547, when the wet-etching process is performed using the solution including hydrofluoric acid, if the solution being highly capable of removing residual substances of metal and/or metal silicide is used, a phenomenon of side-etching of a metal film occurs during the process, which also makes it impossible to maintain a desired pattern shape of the metal film.
Furthermore, when a sputter-etching process using plasma of inert gas such as argon is performed, in order to prevent the degradation of a peeling property caused by damage in a resist, removal of the resist before the sputter-etching process is required. At this point of time, a surface portion of a metal film in a region to be left as a pattern without being etched at the time of sputter-etching process is erroneously etched. Since anisotropy is very strong in the sputter-etching, in a place where steps exist, removal of residual substances existing on a side of the step portion is difficult.